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  data sheet may 1998 T7689 5.0 v t1 quad line interface features n four fully integrated t1 line interfaces n includes all driver, receiver, equalization, clock recovery, and jitter attenuation functions n ultralow power consumption n robust operation for increased system margin n high interference immunity n on-chip transmit equalization for improved sensitivity n low-impedance drivers for reduced power consumption n selectable transmit or receive, jitter attenuation/ clock smoothing n 3-state transmit drivers n high-speed, microprocessor interface n automatic transmit monitor function n per-channel powerdown n for use in systems that are compliant with at&t cb119; tr-tsy-000170, tr-tsy-000009, tr- tsy-000499, tr-tsy-000253; ansi t1.102 and t1.403 n common transformer for transmit/receive n fine-pitch (25 mil spacing) surface-mount package, 100-pin bumpered quad ?t pack n ?0 c to +85 c operating temperature range applications n sonet/sdh multiplexers n asynchronous multiplexers (m13) n digital access cross connects (dacs) n channel banks n digital radio base stations, remote wireless modules n pbx interfaces description the T7689 is a fully integrated quad line interface containing four transmit and receive channels for use in north american (t1/ds1) applications. the device has many of the same functions as the lucent tech- nologies microelectronics group t7290a and pro- vides additional ?xibility for the system designer. included is a parallel microprocessor interface that allows the user to de?e the architecture, initiate loopbacks, and monitor alarms. the interface is com- patible with many commercially available micropro- cessors. the receiver performs clock and data recovery using a fully integrated digital phase-locked loop. this digi- tal implementation prevents false-lock conditions that are common when recovering sparse data patterns with analog phase-locked loops. equalization cir- cuitry in the receiver guarantees a high level of inter- ference immunity. as an option, the raw sliced data (no retiming) can be output on the receive data pins. transmit equalization is implemented with low- impedance output drivers that provide shaped wave- forms to the transformer, guaranteeing template con- formance. the quad device will interface to the digital cross connect (dsx) at lengths of up to 655 ft. for ds1 operation. a selectable jitter attenuator may be placed in the receive signal path for low-bandwidth line- synchronous applications, or it may be placed in the transmit path for multiplexer applications where ds1 signals are demultiplexed from higher rate signals. the jitter attenuator will perform the clock smoothing required on the resulting demultiplexed gapped clock.
2 table of contents contents page contents page lucent technologies inc. data sheet T7689 5.0 v t1 quad line interface may 1998 features .................................................................... 1 applications ............................................................... 1 description ................................................................. 1 block diagram ........................................................... 3 pin information .......................................................... 4 system interface pin options ................................ 9 receiver .................................................................. 10 data recovery ..................................................... 10 jitter ..................................................................... 10 receiver configuration modes ............................ 10 clock/data recovery mode (cdr) ................... 10 zero substitution decoding (code) ................. 10 alternate logic mode (alm) ............................. 10 alternate clock mode (acm) ............................ 11 loss shut down (lossd) ................................ 11 receiver alarms .................................................. 11 analog loss of signal (alos) alarm ................ 11 digital loss of signal (dlos) alarm ................. 11 bipolar violation (bpv) alarm ........................... 11 ds1 receiver specifications ............................... 12 transmitter .............................................................. 13 output pulse generation ..................................... 13 jitter ..................................................................... 13 transmitter configuration modes ........................ 14 zero substitution encoding/decoding (code) ............................................................ 14 all ones (ais, blue signal) generator (tbs) ... 14 transmitter alarms .............................................. 14 loss of transmit clock (lotc) alarm .............. 14 transmit driver monitor (tdm) alarm ............... 14 ds1 transmitter pulse template and specifications ..................................................... 15 jitter attenuator ....................................................... 16 data delay ........................................................... 16 generated (intrinsic) jitter ................................... 16 jitter transfer function ........................................ 16 jitter tolerance .................................................... 16 jitter attenuator enable ....................................... 16 jitter attenuator receive path enable (jar) .... 17 jitter attenuator transmit path enable (jat) ... 17 loopbacks ............................................................... 17 full local loopback (flloop) ........................... 17 remote loopback (rloop) ................................ 17 digital local loopback (dlloop) ....................... 17 other features ........................................................ 18 powerdown (pwrdn) ......................................... 18 reset ( reset , swreset) ............................... 18 loss of xclk reference clock (loxc) .............. 18 in-circuit testing and driver 3-state (ict ) .......... 18 microprocessor interface ......................................... 19 overview .............................................................. 19 microprocessor configuration modes .................. 19 microprocessor interface pinout definitions ........ 20 microprocessor clock (mpclk) specifications ... 21 internal chip select function ............................... 21 microprocessor interface register architecture ... 21 alarm register overview (0000, 0001) ............. 23 alarm mask register overview (0010, 0011) ... 23 global control register overview (0100, 0101) ..................................... 24 channel configuration register overview (0110?001) ................................... 25 other registers ................................................. 25 i/o timing ............................................................ 26 xclk reference clock ............................................ 31 power supply bypassing ......................................... 31 external line interface circuitry .............................. 32 absolute maximum ratings ..................................... 33 handling precautions .............................................. 33 operating conditions ............................................... 33 timing characteristics ............................................. 34 outline diagram ....................................................... 36 100-pin bqfp ...................................................... 36 ordering information ................................................ 37 ds98-232tic replaces ds96-185tic to incorporate the following updates .............................................. 37
data sheet may 1998 T7689 5.0 v t1 quad line interface 3 lucent technologies inc. block diagram the T7689 block diagram is shown in figure 1. for illustration purposes, only one of the four on-chip line interfaces is shown. pin names that apply to all four channels are followed by the designation [1?]. 5-3683(c)r.7 * function can be bypassed by using the microprocessor interface. figure 1. block diagram (single channel) flloop (no blue signal) dlos clock/data recovery* slicers equalizer alos jitter attenuator* (transmit or receive path) bpv decoder* lotc tdm pulse- width controller pulse equalizer encoder* blue signal (ais) loxc ? 16 jitter attenuator* (transmit or receive path) microprocessor interface rnd/bpv[1?] rclk/alos[1?] rtip[1?] rring[1?] xclk xclk tclk[1?] tpd/tdata[1?] bclk ttip[1?] tring[1?] loxc xclk xclk mpclk mpmode mpmux cs ale_as rd_r/w wr_ds int rdy_dtack ad[7:0] a[3:0] flloop (during blue signal) drivers tnd[1?] rpd/rdata[1?] system inter- face line inter- face dlloop rloop
data sheet T7689 5.0 v t1 quad line interface may 1998 4 lucent technologies inc. pin information 5-3684(f).ar4 figure 2. pin diagram 14 16 25 20 22 23 29 18 26 24 28 27 30 31 32 15 17 21 19 11 9 7 98 3 1 100 94 5 97 99 95 96 93 92 91 10 8 6 2 4 41 43 45 54 49 51 52 58 47 55 53 57 56 59 60 61 42 44 46 50 48 86 84 82 73 78 76 75 69 80 72 74 70 71 68 67 66 85 83 81 77 79 tpd1/tdata1 tnd1 tclk1 rpd1/rdata1 rnd1/bpv1 rclk1/alos1 reset rclk4/alos4 rnd4/bpv4 rpd4/rdata4 tclk4 tnd4 tpd4/tdata4 tring3 v dd x3 ttip3 gndx3 tpd2/tdata2 tnd2 tclk2 rpd2/rdata2 rnd2/bpv2 rclk2/alos2 ict v dda 3 gnd a 3 rtip3 rring3 rclk3/alos3 rnd3/bpv3 rpd3/rdata3 tclk3 tnd3 tpd3/tdata3 a0 a1 a2 a3 cs ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 v ddc xclk bclk gnd c microprocessor & control mpclk mpmode rdy_dt a ck int wr _ds rd _r/w ale_as mpmux loxc 62 63 65 64 33 34 39 40 88 87 13 12 90 89 35 36 37 38 gndx3 gnd d 3 v ddd 3 tring2 v dd x2 ttip2 gndx2 v dda 2 gnd a 2 rtip2 rring2 gndx2 gnd d 2 v ddd 2 tring4 v dd x4 ttip4 gndx4 v dda 4 gnd a 4 rring4 rtip4 gndx4 gnd d 4 v ddd 4 tring1 v dd x1 ttip1 gndx1 v dda 1 gnd a 1 rtip1 rring1 gndx1 gnd d 1 v ddd 1 gnd c v ddc t r channel 2 t r channel 1 gnd s gnd s t r channel 4 t r channel 3
data sheet may 1998 T7689 5.0 v t1 quad line interface 5 lucent technologies inc. pin information (continued) table 1. pin descriptions pin symbol type * name/description 1, 51 gnd s p ground reference for substrate . 2, 6 gndx1 p ground reference for line drivers. 46, 50 gndx2 52, 56 gndx3 96, 100 gndx4 3 ttip1 o transmit bipolar tip . positive bipolar transmit output data to the analog line interface. 49 ttip2 53 ttip3 99 ttip4 4v dd x1 p power supply for line drivers. the T7689 device requires a 5 v 5% power supply on these pins. 48 v dd x2 54 v dd x3 98 v dd x4 5 tring1 o transmit bipolar ring . negative bipolar transmit output data to the analog line interface. 47 tring2 55 tring3 97 tring4 7v dda 1p power supply for analog circuitry . the T7689 device requires a 5 v 5% power supply on these pins. 45 v dda 2 57 v dda 3 95 v dda 4 8 rtip1 i receive bipolar tip . positive bipolar receive input data from the analog line interface. 44 rtip2 58 rtip3 94 rtip4 9 rring1 i receive bipolar ring . negative bipolar receive input data from the analog line interface. 43 rring2 59 rring3 93 rring4 10 gnd a 1p ground reference for analog circuitry . 42 gnd a 2 60 gnd a 3 92 gnd a 4 * p = power, i = input, o = output, and i u = input with internal pull-up.
data sheet T7689 5.0 v t1 quad line interface may 1998 6 lucent technologies inc. 11 gnd d 1p ground reference for digital circuitry . 41 gnd d 2 61 gnd d 3 91 gnd d 4 12 v ddd 1p power supply for digital circuitry . the T7689 device requires a 5 v 5% power supply on these pins. 40 v ddd 2 62 v ddd 3 90 v ddd 4 13 rnd1/bpv1 o receive negative data. when in dual-rail (dual = 1: register 5, bit 4) clock recovery mode (cdr = 1: register 5, bit 0), this signal is the receive negative nrz output data to the terminal equipment. when in data slicing mode (cdr = 0), this signal is the raw sliced negative output data of the front end. bipolar violation. when in single-rail (dual = 0: register 5, bit 4) clock recovery mode (cdr = 1: register 5, bit 0), and code = 1 (register 5, bit 3), this signal is asserted high to indicate the occurrence of a code violation in the receive data stream. if code = 0, this signal is asserted to indicate the occurrence of a bipolar violation in the receive data system. 39 rnd2/bpv2 63 rnd3/bpv3 89 rnd4/bpv4 14 rpd1/ r data 1 o receive positive data. when in dual-rail (dual = 1: register 5, bit 4) clock recovery mode (cdr = 1: register 5, bit 0), this signal is the receive positive nrz output data to the terminal equipment. when in data slicing mode (cdr = 0), this signal is the raw sliced positive output data of the front-end. receive data. when in single-rail (dual = 0: register 5, bit 4) clock recov- ery mode (cdr = 1: register 5, bit 0), this signal is the receive nrz output data. 38 rpd2/ r data 2 64 rpd3/ r data 3 88 rpd4/ r data 4 15 rclk1/ alos1 o receive clock. in clock recovery mode (cdr = 1: register 5, bit 0), this sig- nal is the receive clock for the terminal equipment. the duty cycle of rclk is 50% 5%. analog loss of signal. in data slicing mode (cdr = 0: register 5, bit 0), this signal is asserted high to indicate low amplitude receive data at the rtip/rring inputs. 37 rclk2/ alos2 65 rclk3/ alos3 87 rclk4/ alos4 16 tnd1 i transmit negative data. transmit negative nrz input data from the termi- nal equipment. 36 tnd2 66 tnd3 86 tnd4 table 1. pin descriptions (continued) pin symbol type * name/description * p = power, i = input, o = output, and i u = input with internal pull-up. pin information (continued)
data sheet may 1998 T7689 5.0 v t1 quad line interface 7 lucent technologies inc. 17 tpd1/ t data 1 i transmit positive data. when in dual-rail mode (dual = 1: register 5, bit 4), this signal is the transmit positive nrz input data from the terminal equipment. transmit data. when in single-rail mode (dual = 0: register 5, bit 4), this signal is the transmit nrz input data from the terminal equipment. 35 tpd2/ t data 2 67 tpd3/ t data 3 85 tpd4/ t data 4 18 tclk1 i transmit clock. ds1 (1.544 mhz 32 ppm). clock signal from the terminal equipment. 34 tclk2 68 tclk3 84 tclk4 19 wr _ds i write (active-low) . if mpmode = 1 (pin 21), this pin is asserted low by the microprocessor to initiate a write cycle. data strobe (active-low) . if mpmode = 0 (pin 21), this pin becomes the data strobe for the microprocessor. when r/w = 0 (write), a low applied to this pin latches the signal on the data bus into internal registers. 20 mpmux i microprocessor multiplex mode . setting mpmux = 1 allows the micropro- cessor interface to accept multiplexed address and data signals. setting mpmux = 0 allows the microprocessor interface to accept demultiplexed (separate) address and data signals. 21 mpmode i microprocessor mode . when mpmode = 1, the device uses the address latch enable type microprocessor read/write protocol with separate read and write controls. setting mpmode = 0 allows the device to use the address strobe type microprocessor read/write protocol with a separate data strobe and a combined read/write control. 22 rd _r/w i read (active-low) . if mpmod = 1 (pin 21), this pin is asserted low by the microprocessor to initiate a read cycle. read/write . if mpmode = 0 (pin 21), this pin is asserted high by the micro- processor to indicate a read cycle or asserted low to indicate a write cycle. 23 ale_as i address latch enable . if mpmode = 1 (pin 21), this pin becomes the address latch enable for the microprocessor. when this pin transitions from high to low, the address bus inputs are latched into the internal registers. address strobe (active-low) . if mpmode = 0 (pin 21), this pin becomes the address strobe for the microprocessor. when this pin transitions from high to low, the address bus inputs are latched into the internal registers. 24 cs i u chip select (active-low) . this pin is asserted low by the microprocessor to enable the microprocessor interface. if mpmux = 1 (pin 20), cs can be externally tied low to use the internal chip selection function (see the inter- nal chip select function section). an internal 100 k w pull-up is on this pin. table 1. pin descriptions (continued) pin symbol type * name/description * p = power, i = input, o = output, and i u = input with internal pull-up. pin information (continued)
data sheet T7689 5.0 v t1 quad line interface may 1998 8 lucent technologies inc. 25 int o interrupt . this pin is asserted high to indicate an interrupt produced by an alarm condition in register 0 or 1. the activation of this pin can be masked by microprocessor registers 2, 3, and 4. 26 rdy_dt a ck o ready . if mpmode = 1 (pin 21), this pin is asserted high to indicate the device has completed a read or write operation. this pin is in a 3-state con- dition when cs (pin 24) is high. data transfer acknowledge (active-low). if mpmode = 0 (pin 21), this pin is asserted low to indicate the device has completed a read or write operation. 27, 78 gnd c p ground reference for microprocessor interface and control circuitry . 28, 77 v ddc p power supply for microprocessor interface and control circuitry. the T7689 device requires a 5 v 5% power supply on these pins. 29 xclk i u reference clock . a valid reference clock (24.704 mhz 100 ppm for ds1 operation) must be provided at this input for certain applications (see the xclk reference clock section). xclk must be an independent, continu- ously active, ungapped, and unjittered clock to guarantee device perfor- mance speci?ations. an internal 100 k w pull-up is on this pin. 30 bclk i u blue clock . input clock signal used to transmit the blue signal (all 1s data pattern). in ds1 mode, this clock is 1.544 mhz 32 ppm. an internal 100 k w pull-up is on this pin. 31 loxc o loss of xclk . this pin is asserted high when the xclk signal (pin 29) is not present. 32 reset i u hardware reset (active-low) . if reset is forced low, all internal states in the line interface paths are reset and data ?w through each channel will be momentarily disrupted (see the reset ( reset , swreset) section). the reset pin must be held low for a minimum of 10 m s. an internal 50 k w pull- up is on this pin. 33 ict i u in-circuit test control (active-low) . if ict is forced low, certain output pins are placed in a high-impedance state (see the in-circuit testing and driver 3-state (ict ) section). an internal 50 k w pull-up is on this pin. 69 ad7 i/o microprocessor interface address/data bus. if mpmux = 0 (pin 20), these pins become the bidirectional, 3-statable data bus. if mpmux = 1, these pins become the multiplexed address/data bus. in this mode, only the lower 4 bits (ad[3:0]) are used for the internal register addresses. 70 ad6 71 ad5 72 ad4 73 ad3 74 ad2 75 ad1 76 ad0 table 1. pin descriptions (continued) pin symbol type * name/description * p = power, i = input, o = output, and i u = input with internal pull-up. pin information (continued)
data sheet may 1998 T7689 5.0 v t1 quad line interface 9 lucent technologies inc. system interface pin options the system interface can be con?ured to operate in a number of different modes, as shown in table 2. dual-rail or single-rail operation is possible using the dual control bit (register 5, bit 4). dual-rail mode is enabled when dual = 1; single-rail mode is enabled when dual = 0. in dual-rail operation, data received from the line interface on rtip and rring appears on rpd (pins 14, 38, 64, 88) and rnd (pins 13, 39, 63, 89) at the system interface and data transmitted from the system interface on tpd (pins 17, 35, 67, 85) and tnd (pins 16, 36, 66, 86) appears on ttip and tring at the line interface. in single-rail operation, data received from the line interface on rtip and rring appears on rdata (pins 14, 38, 64, 88) at the system interface and data transmitted from the system inter- face on tdata (pins 17, 35, 67, 85) appears on ttip and tring at the line interface. in both dual-rail and single-rail operation, the clock/data recovery mode is selectable via the cdr bit (register 5, bit 0). when cdr = 1, the clock and data recovery is enabled and the system interface operates in a nonreturn to zero (nrz) digital format. when cdr = 0, the clock and data recovery is disabled and the system interface oper- ates on unretimed sliced data in rz data format (see the data recovery section). in single-rail mode only, b8zs encoding/decoding may be selected by setting code = 1 (register 5, bit 3). this allows coding violations, such as receiving two consecutive 1s of the same polarity from the line interface, to be output on bpv (pins 13, 39, 63, 89) (see the zero substitution encoding/decoding (code) section). 79 a3 i microprocessor interface address. if mpmux = 0 (pin 20), these pins become the address bus for the microprocessor interface registers. if mpmux = 1, a3 (pin 79) can be externally tied high to use the internal chip selection function (see the internal chip select function section). if this function is not used, a[3:0] must be externally tied low. 80 a2 81 a1 82 a0 83 mpclk i microprocessor interface clock. microprocessor interface clock rates from twice the frequency of the line clock (3.088 mhz for ds1 operation) to 16.384 mhz are supported. table 2. pin mapping con?uration rclk/ alos rpd/ rdata rnd/bpv tpd/ tdata tnd dual-rail system interface with clock recovery rclk rpd rnd tpd tnd dual-rail system interface with data slicing only alos rpd rnd single-rail system interface with clock recovery rclk rdata bpv t data not used single-rail system interface with data slicing only alos rpd rnd table 1. pin descriptions (continued) pin symbol type * name/description * p = power, i = input, o = output, and i u = input with internal pull-up. pin information (continued)
data sheet T7689 5.0 v t1 quad line interface may 1998 10 lucent technologies inc. receiver data recovery the receive line interface transmission format of the device is bipolar alternate mark inversion (ami). it accepts input data with a frequency tolerance of 130 ppm (ds1). the receiver ?st restores the incom- ing data and detects analog loss of signal. subsequent processing is optional and depends on the programma- ble device con?uration established within the micro- processor interface registers. the receiver operates with high interference immunity, utilizing an equalizer to restore fast rise/fall times following maximum cable loss. the signal is then peak-detected and sliced to produce digital representations of the data. selectable clock recovery of the sliced data, digital loss of signal, jitter attenuation, and data decoding are per- formed. for applications bypassing the clock recovery function (cdr = 0), the receive digital output format is unretimed sliced data (rz positive and negative data). for clock recovery applications (cdr = 1), the receive digital output format is nonreturn to zero (nrz) with selectable dual-rail or single-rail system interface. the recovered clock (rclk, pins 15, 37, 65, 87) is only pro- vided when cdr = 1 (see table 2). timing recovery is performed by a digital phase-locked loop that uses xclk (pin 29) as a reference to lock to the incoming data. because the reference clock is a multiple of the received data rate, the output rclk (pins 15, 37, 65, 87) will always be a valid ds1 clock that eliminates false-lock conditions. during periods with no input signal, the free-run frequency is de?ed to be xclk/16. rclk is always active with a duty-cycle centered at 50%, deviating by no more than 5%. valid data is recovered within the ?st few bit periods after the application of xclk. the delay of the data through the receive circuitry is approximately 1 bit to 14 bit peri- ods, depending on the cdr and code con?urations. additional delay is introduced if the jitter attenuator is selected for operation in the receive path (see the data delay section). jitter the receiver is designed to accommodate large amounts of input jitter. the receiver jitter performance far exceeds the requirements shown in table 4. jitter transfer is independent of input ones density on the line interface. high-frequency jitter tolerance is a minimum of 0.4 unit intervals (ui). receiver con?uration modes clock/data recovery mode (cdr) the clock/data recovery function in the receive path is selectable via the cdr bit (register 5, bit 0). if cdr = 1, the clock and data recovery function is enabled and provides a recovered clock (rclk) with retimed data (rpd/rdata, rnd). if cdr = 0, the clock and data recovery function is disabled, and the rz data from the slicers is provided over rpd and rnd to the system. in this mode, alos is available on the rclk/alos pins, and downstream functions selected by microprocessor register 5 (jar, acm, lossd) are ignored. zero substitution decoding (code) when single-rail operation is selected with dual = 0 (register 5, bit 4), the b8zs zero substitution decoding can be selected via the code bit (register 5, bit 3). if code = 1, the b8zs decoding function is enabled in the receive path and decoded receive data and code violations appear on the rdata and bpv pins, respec- tively. if code = 0, receive data and any bipolar viola- tions (such as two consecutive 1s of the same polarity) appear on the rdata and bpv pins, respectively. alternate logic mode (alm) the alternate logic mode (alm) control bit (register 5, bit 5) selects the receive and transmit data polarity (i.e., active-high vs. active-low). if alm = 0, the receiver cir- cuitry (and transmit input) assumes the data to be active-low polarity. if alm = 1, the receiver circuitry (and transmit input) assumes the data to be active-high polarity. the alm control is used in conjunction with the acm control (register 5, bit 6) to determine the receive data retiming mode.
data sheet may 1998 T7689 5.0 v t1 quad line interface 11 lucent technologies inc. receiver (continued) receiver con?uration modes (continued) alternate clock mode (acm) the alternate clock mode (acm) control bit (register 5, bit 6) selects the positive or negative clock edge of the receive clock (rclk) for receive data retiming. the acm control is used in conjunction with alm (register 5, bit 5) control to determine the receive data retiming modes. if acm = 1, the receive data is retimed on the positive edge of the receive clock. if acm = 0, the receive data is retimed on the negative edge of the receive clock. note that this control does not affect the timing relationship for the transmitter inputs. loss shut down (lossd) the loss shut down (lossd) control bit (register 5, bit 7) places the digital receiver outputs (rpd, rnd) in a predetermined state when a digital loss of signal (dlos) alarm occurs in register 0 and 1, bits 1 and 5. if lossd = 1, the rpd and rnd outputs are forced to their inactive states (selected by alm) and the receive clock (rclk) free runs during a dlos alarm condition. if lossd = 0, the rpd, rnd, and rclk outputs will remain unaffected during the dlos alarm condition. receiver alarms analog loss of signal (alos) alarm an analog loss of signal (alos) detector monitors the incoming signal amplitude and reports its status to the alarm registers 0 and 1. during ds1 operation, analog loss of signal is indicated (alos = 1) if the amplitude at the receive input drops below a voltage that is 17 db below the nominal pulse amplitude. the slicer outputs are clamped to the inactive state, and the clock recovery will provide a free-running rclk when alos = 1. the alarm circuitry also provides 4 db of hysteresis to eliminate alos chattering. the time required to detect alos is between 1 ms and 2.6 ms and is timed by the blue clock (see the all ones (ais, blue signal) generator (tbs) section). detection time is independent of signal amplitude before the loss con- dition occurs. digital loss of signal (dlos) alarm a digital loss of signal (dlos) detector guarantees the quality of the signal as de?ed in standards docu- ments, and reports its status to the alarm registers 0 and 1. digital loss of signal (dlos = 1) is indicated if 100 or more consecutive 0s occur in the receive data stream. the dlos indication is deactivated when the average ones density of at least 12.5% is received in 100 contiguous pulse positions. the losstd control bit (register 4, bit 2) selects the conformance protocols for dlos per table 3. tr-tsy-000009 adds the addi- tional constraint of no more than 15 consecutive 0s when determining the 12.5% 1s density. bipolar violation (bpv) alarm the bipolar violation (bpv) alarm is used only in single- rail mode of operation of the device (see the system interface pin options section). when b8zs(ds1) cod- ing is not used (i.e., code = 0), any violations in the receive data (such as two or more consecutive 1s on a rail) are indicated on the rnd/bpv pins. when b8zs(ds1) coding is used (i.e., code = 1), the b8zs code violations are re?cted on the rnd/bpv pins. table 3. digital loss of signal standard select losstd ds1 mode 0 t1m1.3/93-005 itu-t g.775 1 tr-tsy-000009
data sheet T7689 5.0 v t1 quad line interface may 1998 12 lucent technologies inc. receiver (continued) ds1 receiver speci?ations during ds1 operation, the receiver will perform as speci?d in table 4. * below the nominal pulse amplitude of 3.0 v using external line interface circuitry described in figure 12 and table 21. ? amount of cable loss. using external line interface circuitry described in figure 12 and table 21. table 4. ds1 receiver speci?ations parameter min typ max unit speci?ation analog loss of signal: threshold hysteresis 20 17 4 db* db maximum sensitivity ? 11 15 db jitter transfer: 3 db bandwidth peaking 3.84 0.1 khz db tr-tsy-000499 generated jitter 0.032 0.04 ui pk-pk tr-tsy-000499, itu-t g.824 jitter tolerance itu-t g.823-4, tr-tsy-000009, tr-tsy-000499, tr-tsy-000170 return loss : 51 khz to 102 khz 102 khz to 1.544 mhz 1.544 mhz to 2.316 mhz 14 20 16 db db db digital loss of signal: flag asserted, consecutive bit positions flag deasserted data density maximum consecutive zeros 100 12.5 15 99 zeros % ones zeros zeros tr-tsy-000009 itu-t g.775, t1m1.3/93-005
data sheet may 1998 T7689 5.0 v t1 quad line interface 13 lucent technologies inc. transmitter output pulse generation the transmitter accepts a clock with nrz data in single-rail mode (dual = 0: register 5, bit 4) or positive and neg- ative nrz data in dual-rail mode (dual = 1) from the system. the device converts this data to a balanced bipolar signal (ami format) with optional b8zs(ds1) encoding and jitter attenuation. low-impedance output drivers pro- duce these pulses on the line interface. positive 1s are output as a positive pulse on ttip, and negative 1s are out- put as a positive pulse on tring. binary 0s are converted to null pulses. the total delay of the data from the system interface to the transmit driver is approximately 3 to 11 bit periods, depending on the code (register 5, bit 3) con?uration. additional delay results if the jitter attenuator is selected for use in the transmit path (see the data delay section). transmit pulse shaping is controlled by the on-chip pulse-width controller and pulse equalizer. the pulse-width controller produces the high-speed timing signals to accurately control the transmit pulse widths. this eliminates the need for a tightly controlled transmit clock duty cycle that is usually required in discrete implementations. the pulse equalizer controls the amplitudes of these pulse shapes. different pulse equalizations are selected through proper settings of eqa, eqb, and eqc (registers 6 to 9, bits 5 to 7) as described in table 5. * other logical settings of eqa, eqb, and eqc should not be used. ? in ds1 mode, the distance to the dsx for 22 gauge pic (abam) cable is speci?d. use the maximum cable loss ?ures for other cable types. loss measured at 772 khz. jitter the intrinsic jitter of the transmit path, i.e., the jitter at ttip/tring when no jitter is applied to tclk (and the jitter attenuator is not selected, jat = 0), is typically 5 ns pk-pk and will not exceed 0.02 ui pk-pk . table 5. equalizer/rate control eqa * eqb * eqc * service clock rate transmitter equalization ? maximum cable loss feet meters db 000 ds1 1.544 mhz 0 ft. to 131 ft. 0 m to 40 m 0.6 0 0 1 131 ft. to 262 ft. 40 m to 80 m 1.2 0 1 0 262 ft. to 393 ft. 80 m to 120 m 1.8 0 1 1 393 ft. to 524 ft. 120 m to 160 m 2.4 1 0 0 524 ft. to 655 ft. 160 m to 200 m 3.0
data sheet T7689 5.0 v t1 quad line interface may 1998 14 lucent technologies inc. transmitter (continued) transmitter con?uration modes zero substitution encoding/decoding (code) zero substitution encoding/decoding (b8zs) can be activated only in the single-rail system interface mode (dual = 0) by setting code = 1 (register 5, bit 3). data received from the line interface on rtip and rring will be b8zs decoded before appearing on rdata (pins 14, 38, 64, 88) at the system interface. likewise, data transmitted from the system interface on tdata (pins 17, 35, 67, 85) will be b8zs encoded before appearing on ttip and tring at the line inter- face. this mode also allows coding violations, such as receiving two consecutive 1s of the same polarity from the line interface, to be output on bpv (pins 13, 39, 63, 89). all ones (ais, blue signal) generator (tbs) when the transmit blue signal control is set (tbs = 1) for a given channel (registers 6 to 9, bit 2), a continu- ous stream of bipolar 1s is transmitted to the line inter- face (ais). the tpd/tdata and tnd inputs are ignored during this mode. the tbs input is ignored when a remote loopback (rloop) is selected using loopback control bits loopa and loopb (registers 6 to 9, bits 3 and 4). (see the loopbacks section.) to maintain application ?xibility, the clock source used for the blue signal is selected by con?uring bclk (pin 30). if a data rate clock is input on the bclk pin, it will be used to transmit the blue signal. if bclk = 0, then tclk is used to transmit the blue signal (the smoothed clock from the jitter attenuator is used if jat = 1 is selected). if bclk = 1, then xclk (after being divided by a factor of 16) is used to transmit the blue signal. after bclk is established, a minimum of 16 m s is required for the device to properly select the clock. for any of the above options, the clock tolerance must meet the normal line transmission rate (ds1 1.544 mhz 32 ppm). transmitter alarms loss of transmit clock (lotc) alarm a loss of transmit clock alarm (lotc = 1) is indicated if any of the clocks in the transmit path disappear (regis- ters 0 and 1, bits 3 and 7). this includes loss of tclk input, loss of rclk during remote loopback, loss of jit- ter attenuator output clock (when enabled), or the loss of clock from the pulse-width controller. for all of these conditions, a core transmitter timing clock is lost and no data can be driven onto the line. output drivers ttip and tring are placed in a high- impedance state when this alarm condition is active. the lotc interrupt is asserted between 3 m s and 16 m s after the clock disappears, and deasserts imme- diately after detecting the ?st clock edge. transmit driver monitor (tdm) alarm the transmit driver monitor detects two conditions: a nonfunctional link due to faults on the primary of the transmit transformer, and periods of no data transmis- sion. the tdm alarm (registers 0 and 1, bits 2 and 6) is the ored function of both faults and provides informa- tion about the integrity of the transmit signal path. the ?st monitoring function is provided to detect non- functional links and protect the device from damage. the alarm is set (tdm = 1) when one of the transmit- ter's line drivers (ttip or tring) is shorted to power supply or ground, or ttip and tring are shorted together. under these conditions, internal circuitry pro- tects the device from damage and excessive power supply current consumption by 3-stating the output drivers. the monitor detects faults on the transformer primary, but transformer secondary faults may not be detected. the monitor operates by comparing the line pulses with the transmit inputs as in a bit error detect mode. after 32 transmit clock cycles, the transmitter is powered up in its normal operating mode. the drivers attempt to correctly transmit the next data bit. if the error persists, tdm remains active to eliminate alarm chatter and the transmitter is internally protected for another 32 transmit clock cycles. this process is repeated until the error condition is removed and the tdm alarm is deactivated. the second monitoring function is to indicate periods of no data transmission. the alarm is set (tdm = 1) when 32 consecutive zeros have been transmitted and is cleared on the detection of a single pulse. this alarm condition does not alter the state or functionality of the signal path.
data sheet may 1998 T7689 5.0 v t1 quad line interface 15 lucent technologies inc. transmitter (continued) ds1 transmitter pulse template and speci- ?ations the ds1 pulse shape template is speci?d at the dsx (de?ed by cb119 and ansi t1.102) and is illustrated in figure 3. the device also meets the pulse template speci?d by itu-t g.703 (not shown). 5-1160(c)r.6 figure 3. dsx-1 isolated pulse template normalized amplitude (a) 1.0 0.5 0 ?.5 0 250 500 750 1000 1250 time (ns) during ds1 operation, the transmitter tip/ring (ttip/ tring pins) will perform as speci?d in table 7. table 6. dsx-1 pulse template corner points (from cb119) maximum curve minimum curve nsvnsv 0 250 325 325 425 500 675 725 1100 1250 0.05 0.05 0.80 1.15 1.15 1.05 1.05 ?.07 0.05 0.05 0 350 350 400 500 600 650 650 800 925 1100 1250 ?.05 ?.05 0.50 0.95 0.95 0.90 0.50 ?.45 ?.45 ?.20 ?.05 ?.05 * in accordance with the interfaces described in the absolute maximum ratings section and the handling precautions section, measured at the transformer secondary. ? total power difference. measured in a 2 khz band around the speci?d frequency. below the power at 772 khz. table 7. ds1 transmitter speci?ations parameter min typ max unit speci?ation output pulse amplitude at dsx* 2.5 2.8 3.5 v at&t cb119, ansi t1.102 output pulse width 338 350 362 ns positive/negative pulse imbalance ? 0.1 0.4 db power levels: 772 khz 1.544 mhz 12.6 29 39 17.9 dbm db
data sheet T7689 5.0 v t1 quad line interface may 1998 16 lucent technologies inc. jitter attenuator the selectable jitter attenuator is provided for narrow- bandwidth jitter transfer function applications. the selection is done via control bits which are global and affect all four channels. one application is to provide narrow-bandwidth jitter ?tering for line-synchronization in the receive path. another use of the jitter attenuator is to provide clock smoothing in the transmit signaling path for applications such as synchronous/asynchro- nous demultiplexers. in these applications, tclk will have an instantaneous frequency that is higher than the data rate and periods of tclk are suppressed (gapped) in order to set the average long-term tclk frequency to within the transmit line rate speci?ation. the jitter attenuator does not degrade the jitter speci? cations of the receiver clock/data recovery circuit. in addition, the jitter attenuator must meet the speci?a- tions for narrow-bandwidth applications as listed in table 8. data delay providing narrow-bandwidth jitter ?tering requires data buffering to increase the data delay through the jitter attenuator. the nominal data delay for the jitter attenua- tor is 33 bit periods, with a maximum data delay of 66 bit periods. this delay is dependent on the input clock frequency, xclk frequency, input jitter, and gapped clock patterns. generated (intrinsic) jitter generated jitter is the amount of jitter appearing on the output port when the applied input signal has no jitter. the jitter attenuator of this device outputs a maximum of 0.04 u.i. peak-to-peak intrinsic jitter. jitter transfer function the jitter transfer function describes the amount of jitter in speci? equipment that is transferred from the input to the output over a frequency range. the jitter attenua- tor exhibits a single-pole rolloff (20 db/decade) jitter transfer characteristic that has no peaking and a nomi- nal ?ter corner frequency (3 db bandwidth) for ds1 operation of less than 10 hz. for a given frequency, dif- ferent jitter amplitudes will cause slight variations in attenuation because of ?ite quantization effects. jitter amplitudes of less than approximately 0.2 u.i. will have greater attenuation than the single-pole rolloff charac- teristic. measurement of the jitter transfer function involves stimulating the circuit with a sinusoidal jitter test signal. the difference between the output signal power and the test signal power, at a given frequency, is the jitter transfer. when output signal power is below the noise ?or, it cannot be measured. halting the jitter transfer function measurements because of noise ?or limita- tions is acceptable during conformance testing. jitter tolerance the minimum jitter tolerance of the jitter attenuator occurs when the xclk frequency and the long-term average frequency of the input clock are at their extreme frequency tolerances. the minimum tolerance is 28 u.i. peak-to-peak at the highest jitter frequency of 15 khz. jitter attenuator enable the jitter attenuator is selected using the jar and jat bits (register 5, bits 1 and 2) of the microprocessor interface. these control bits are global and affect all four channels unless a given channel is in the power- down mode (pwrdn = 1). because there is only one attenuator function in the device, selection must be made between either the transmit or receive path. if both jat and jar are activated at the same time, the jitter attenuator will be disabled. note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active, as described in table 26. if jitter attenuation is selected, a valid xclk (pin 29) signal must be available. table 8. list of low bandwidth jitter speci?ation documents application ds1 tr-tsy-000009 tr-tsy-000253 tr-tsy-000499
data sheet may 1998 T7689 5.0 v t1 quad line interface 17 lucent technologies inc. jitter attenuator (continued) jitter attenuator enable (continued) jitter attenuator receive path enable (jar) when the jitter attenuator receive bit is set (jar = 1), the attenuator is enabled in the receive data path between the clock/data recovery and the decoder (see figure 1). under this condition, the jitter characteristics of the jitter attenuator apply for the receiver. when jar = 0, the clock/data recovery outputs bypass the disabled attenuator and directly enter the decoder func- tion. the receive path will then exhibit the jitter charac- teristics of the clock recovery function as described in the jitter section. if cdr = 0 (register 5, bit 0), the jar bit is ignored because clock recovery will be disabled. jitter attenuator transmit path enable (jat) when the jitter attenuator transmit bit is set (jat = 1), the attenuator is enabled in the transmit data path between the encoder and the pulse-width controller/ pulse equalizer (see figure 1). under this condition, the jitter characteristics of the jitter attenuator apply for the transmitter. when jat = 0, the encoder outputs bypass the disabled attenuator and directly enter the pulse-width controller/pulse equalizer. the transmit path will then pass all jitter from tclk to line interface outputs ttip/tring. loopbacks the device has three independent loopback paths that are activated using loopa and loopb (registers 6 to 9, bits 3 and 4) as shown in table 9. the locations of these loopbacks are illustrated in figure 1. * during the transmit blue signal condition, the looped data will be the transmitted data from the system and not the all-1s signal. ? transmit blue signal request is ignored. full local loopback (flloop) a full local loopback (flloop) connects the transmit line driver input to the receiver analog front-end cir- cuitry. valid transmit output data continues to be sent to the network. if the transmit blue signal (all-1s signal) is sent to the network, the looped data is not affected. the alos alarm continues to monitor the receive line interface signal while dlos monitors the looped data. remote loopback (rloop) a remote loopback (rloop) connects the recovered clock and retimed data to the transmitter at the system interface and sends the data back to the line. the receiver front end, clock/data recovery, encoder/ decoder (if enabled) jitter attenuator (if enabled), and transmit driver circuitry are all exercised during this loopback. the transmit clock, transmit data, and tbs inputs are ignored. valid receive output data continues to be sent to the system interface. this loopback mode is very useful for isolating failures between systems. digital local loopback (dlloop) a digital local loopback (dlloop) connects the trans- mit clock and data through the encoder/decoder pair to the receive clock and data output pins at the system interface. this loopback is operational if the encoder/ decoder pair is enabled or disabled. the blue signal can be transmitted without any effect on the looped sig- nal. table 9. loopback control operation symbol loopa loopb normal 0 0 full local loopback flloop* 0 1 remote loopback rloop ? 10 digital local loopback dlloop 1 1
data sheet T7689 5.0 v t1 quad line interface may 1998 18 lucent technologies inc. other features powerdown (pwrdn) each line interface channel has an independent power- down mode controlled by pwrdn (registers 6 to 9, bit 0). this provides power savings for systems that use backup channels. if pwrdn = 1, the corresponding channel will be in a standby mode, consuming only a small amount of power. it is recommended that the alarm registers for the corresponding channel be masked with mask = 1 (registers 6 to 9, bit 1) during powerdown mode. if a line interface channel in power- down mode needs to be placed into service, the chan- nel should be turned on (pwrdn = 0) approximately 5 ms before data is applied. if a line interface channel will never be in service, the v dda and v ddd pins can be connected to the ground plane, resulting in no power consumption. reset ( reset , swreset) the device provides both a hardware reset ( reset ; pin 32) and a software reset (swreset; register 4, bit 1) that are functionally equivalent. when the device is in reset, all signal-path and alarm monitor states are initialized to a known starting con?uration. the status registers and int (pin 25) are also cleared. the writ- able microprocessor interface registers are not affected by reset, with the exception of bits in register 4 (see the global control register overview (0100, 0101) sec- tion). during a reset condition, data transmission will be momentarily interrupted and the device will respond to those register bits affected by the reset. on powerup of the device, the software reset bit (register 4, bit 1) is not initialized. it must be written to a zero prior to writing the other bits in register 4. the reset condition is initiated by setting reset = 0 or swreset = 1 for a minimum of 10 m s. after leaving the reset condition (with reset = 1 or swreset = 0), only the bits in register 4 need to be restored. loss of xclk reference clock (loxc) the loxc output (pin 31) is active when the xclk ref- erence clock (pin 29) is absent. the loxc ?g is asserted between 150 ns and 700 ns after xclk dis- appears, and deasserts immediately after detecting the ?st clock edge of xclk. during the loxc alarm condition, the clock recovery and jitter attenuator functions are automatically dis- abled. therefore, if cdr = 1 and/or jar = 1, the rclk, rpd, rnd, and dlos outputs will be unknown. if cdr = 0, there will be no effect on the receiver. if the jitter attenuator is enabled in the transmit path (jat = 1) during this alarm condition, then lotc = 1 will also be indicated. in-circuit testing and driver 3-state ( ict ) the function of the ict input (pin 33) is determined by the ictmode bit (register 4, bit 3). if ictmode = 0 and ict is activated ( ict = 0), then all output buffers (ttip, tring, rclk, rpd, rnd, loxc, rdy_ dt a ck , int, ad[7:0]) are placed in a high-impedance state. for in-circuit testing, the reset pin can be used to activate ictmode = 0 without having to write the bit. if ict- mode = 1 and ict = 0, then only the ttip and tring outputs of all channels will be placed in a high- impedance state. the ttip and tring outputs have a limiting high-impedance capability of approximately 8 k w .
data sheet may 1998 T7689 5.0 v t1 quad line interface 19 lucent technologies inc. microprocessor interface overview the device is equipped with a microprocessor interface that can operate with most commercially available microprocessors. inputs mpmux and mpmode (pins 20 and 21) are used to con?ure this interface into one of four possible modes, as shown in table 10. the mpmux setting selects either a multiplexed 8-bit address/data bus (ad[7:0]) or a demultiplexed 4-bit address bus (a[3:0]) and an 8-bit data bus (ad[7:0]). the mpmode setting selects the associated set of control signals required to access a set of registers within the device. when the microprocessor interface is con?ured to operate in the multiplexed address/data bus modes (mpmux = 1), the user has access to an internal chip select function that allows the microprocessor to selec- tively read/write a speci? T7689 in a multiple T7689 environment (see the internal chip select function section). the microprocessor interface can operate at speeds up to 16.384 mhz in interrupt-driven or polled mode without requiring any wait-states. for micropro- cessors operating at greater than 16.384 mhz, the rdy_dt a ck output is used to introduce wait-states in the read/write cycles. in the interrupt-driven mode, one or more device alarms will assert the active-high int output (pin 25) once per alarm activation. after the microprocessor reads the alarm status registers, the int output will deassert. in the polled mode, however, the micropro- cessor monitors the various device alarm status by periodically reading the alarm status registers without the use of int (pin 25). in both interrupt and polled methods of alarm servicing, the status register will clear on a microprocessor read cycle only when the alarm condition within the signaling channel no longer exists; otherwise, the register bit remains set. due to the device ?xibility, there are no default power- up or reset states, except for register 4. all read/write registers must be written by the microprocessor on system start-up to guarantee proper device functional- ity. details concerning microprocessor interface con?ura- tion modes, pinout de?itions, clock speci?ations, register bank architecture, and the i/o timing speci?a- tions and diagrams are described in the following sec- tions. microprocessor con?uration modes table 10 highlights the four microprocessor modes controlled by the mpmux and mpmode inputs (pins 20 and 21). table 10. microprocessor con?uration modes mode mpmode mpmux address/data bus generic control, data, and output pin names mode1 0 0 demuxed cs , as , ds , r/ w , a[3:0], ad[7:0], int, dt a ck mode2 0 1 muxed cs , as , ds , r /w , ad[7:0], int, dt a ck mode3 1 0 demuxed cs , ale, rd , wr , a[3:0], ad[7:0], int, rdy mode4 1 1 muxed cs , ale, rd , wr , ad[7:0], int, rdy
data sheet T7689 5.0 v t1 quad line interface may 1998 20 lucent technologies inc. microprocessor interface (continued) microprocessor interface pinout de?itions the mode1 through mode4 speci? pin de?itions are given in table 11. note that the microprocessor interface uses the same set of pins in all modes. table 11. mode [1?] microprocessor pin de?itions con?uration pin number device pin name generic pin name pin_type assertion sense function mode1 19 wr _ds ds i active-low data strobe 22 rd _r/w r/w i read/write r/w = 1 => read r/w = 0 => write 23 ale_as as i address strobe 24 cs cs i active-low chip select 25 int int o active-high interrupt 26 rdy_dt a ck dt a ck o active-low data acknowledge 69?6 ad[7:0] ad[7:0] i/o data bus 79?2 a[3:0] a[3:0] i address bus 83 mpclk mpclk i microprocessor clock mode2 19 wr _ds ds i active-low data strobe 22 rd _r/w r/w i read/write r/w = 1 => read r/w = 0 => write 23 ale_as as i address strobe 24 cs cs i active-low chip select 25 int int o active-high interrupt 26 rdy_dt a ck dt a ck o active-low data acknowledge 69?6 ad[7:0] ad[7:0] i/o address/data bus 83 mpclk mpclk i microprocessor clock mode3 19 wr _ds wr i active-low write 22 rd _r/w rd i active-low read 23 ale_as ale i address latch enable 24 cs cs i active-low chip select 25 int int o active-high interrupt 26 rdy_dt a ck rdy o active-high ready 69?6 ad[7:0] ad[7:0] i/o data bus 79?2 a[3:0] a[3:0] i address bus 83 mpclk mpclk i microprocessor clock mode4 19 wr _ds wr i active-low write 22 rd _r/w rd i active-low read 23 ale_as ale i address latch enable 24 cs cs i active-low chip select 25 int int o active-high interrupt 26 rdy_dt a ck rdy o active-high ready 69?6 ad[7:0] ad[7:0] i/o address/data bus 83 mpclk mpclk i microprocessor clock
data sheet may 1998 T7689 5.0 v t1 quad line interface 21 lucent technologies inc. microprocessor interface (continued) microprocessor clock (mpclk) speci?ations the microprocessor interface is designed to operate at clock speeds up to 16.384 mhz without requiring any wait- states. wait-states may be needed if higher microprocessor clock speeds are required. the microprocessor clock (mpclk, pin 83) speci?ation is shown in table 12. this clock must be supplied only if the rdy_dt a ck and int outputs are required to be synchronous to mpclk. otherwise, the mpclk pin must be connected to ground (gnd d ). internal chip select function when the microprocessor interface is con?ured to operate in the multiplexed address/data bus modes (mpux = 1), the user has access to an internal chip select function. this function allows a microprocessor to selectively read or write a speci? quad line interface device in a system of up to eight devices on the microprocessor bus. exter- nally tying cs = 0 (pin 24) and a3 = 1 (pin 79) on every line interface device enables the internal chip select func- tion. individual device addresses are established by externally connecting the other three address pins a[2:0] to a unique address value in the range of 000 through 111. in order for a line interface device to respond to the register read or write request from the microprocessor, the address data bus ad[6:4] (pins 70, 71, 72) must match the spe- ci? address de?ed on a[2:0]. if cs and a3 pins are tied low, the internal chip select function is disabled and all line interface devices will respond to a microprocessor write request. however, if cs = 1, none of the line interface devices will respond to the microprocessor read/write request. microprocessor interface register architecture the register bank architecture of the microprocessor interface is shown in table 13. the register bank consists of sixteen 8-bit registers classi?d as alarm registers, global control registers, and channel con?uration/mainte- nance registers. registers 0 and 1 are the alarm registers used for storing the various device alarm status and are read-only. all other registers are read/write. registers 2 and 3 contain the individual mask bits for the alarms in reg- isters 0 and 1. registers 4 and 5 are designated as the global control registers used to set up the functions for all four channels. the channel con?uration registers in registers 6 through 9 are used to con?ure the individual channel functions and parameters. registers 10 and 11 must be cleared by the user after a powerup for proper device operation. registers 12 through 15 are reserved for proprietary functions and must not be addressed during operation. the following sections describe these registers in detail. table 12. microprocessor input clock speci?ations name symbol period and tolerance t rise typ t fall typ duty cycle unit min high min low mpclk t1 61 to 323 5 5 27 27 ns
data sheet T7689 5.0 v t1 quad line interface may 1998 22 lucent technologies inc. microprocessor interface (continued) microprocessor interface register architecture (continued) notes: a numerical suf? appended to the bit name identi?s the channel number. bits shown in parentheses indicate the state forced during a reset condition. all registers must be con?ured by the user before the device can operate as required for the particular application. registers 10 and 11 must be written to zero after powerup of the device. it is recommended that registers 12?5 should be written to 0 after powerup of the device. table 13. register set designation address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 alarm registers (read only) 0 0000 lotc2 tdm2 dlos2 alos2 lotc1 tdm1 dlos1 alos1 1 0001 lotc4 tdm4 dlos4 alos4 lotc3 tdm3 dlos3 alos3 alarm mask registers (read/write) 2 0010 mlotc2 mtdm2 mdlos2 malos2 mlotc1 mtdm1 mdlos1 malos1 3 0011 mlotc4 mtdm4 mdlos4 malos4 mlotc3 mtdm3 mdlos3 malos3 global control registers (read/write) 4 0100 highz4 (1) highz3 (1) highz2 (1) highz1 (1) ictmode (0) losstd swreset gmask (1) 5 0101 lossd acm alm dual code jat jar cdr channel con?uration registers (read/write) 6 0110 eqa1 eqb1 eqc1 loopa1 loopb1 tbs1 mask1 pwrdn1 7 0111 eqa2 eqb2 eqc2 loopa2 loopb2 tbs2 mask2 pwrdn2 8 1000 eqa3 eqb3 eqc3 loopa3 loopb3 tbs3 mask3 pwrdn3 9 1001 eqa4 eqb4 eqc4 loopa4 loopb4 tbs4 mask4 pwrdn4 10 1010 0000 0000 11 1011 0000 0000 12?5 1100?111 reserved
data sheet may 1998 T7689 5.0 v t1 quad line interface 23 lucent technologies inc. microprocessor interface (continued) microprocessor interface register architecture (continued) alarm register overview (0000, 0001) the bits in the alarm registers represent the status of the transmitter and receiver alarms lotc, tdm, dlos, and alos for all four channels as shown in table 14. the alarm indicators are active-high and automatically clear on a microprocessor read if the corresponding alarm condition no longer exists. persistent alarm conditions will cause the bit to remain set. these are read-only registers. * the numerical suf? identi?s the channel number. alarm mask register overview (0010, 0011) the bits in the alarm mask registers in table 15 allow the microprocessor to selectively mask each channel alarm and prevent it from generating an interrupt. the mask bits correspond to the alarm status bits in the alarm registers and are active-high to disable the corresponding alarm from generating an interrupt. these registers are read/write registers. * the numerical suf? identi?s the channel number. table 14. alarm registers bits symbol * description alarm register (0) 0, 4 alos[1:2] analog loss of signal alarm for channels 1 & 2. 1, 5 dlos[1:2] digital loss of signal alarm for channels 1 & 2. 2, 6 tdm[1:2] transmit driver monitor alarm for channels 1 & 2. 3, 7 lotc[1:2] loss of transmit clock alarm for channels 1 & 2. alarm register (1) 0, 4 alos[3:4] analog loss of signal alarm for channels 3 & 4. 1, 5 dlos[3:4] digital loss of signal alarm for channels 3 & 4. 2, 6 tdm[3:4] transmit driver monitor alarm for channels 3 & 4. 3, 7 lotc[3:4] loss of transmit clock alarm for channels 3 & 4. table 15. alarm mask registers bits symbol * description alarm mask register (2) 0, 4 malos[1:2] mask analog loss of signal alarm for channels 1 & 2. 1, 5 mdlos[1:2] mask digital loss of signal alarm for channels 1 & 2. 2, 6 mtdm[1:2] mask transmit driver monitor alarm for channels 1 & 2. 3, 7 mlotc[1:2] mask loss of transmit clock alarm for channels 1 & 2. alarm mask register (3) 0, 4 malos[3:4] mask analog loss of signal alarm for channels 3 & 4. 1, 5 mdlos[3:4] mask digital loss of signal alarm for channels 3 & 4. 2, 6 mtdm[3:4] mask transmit driver monitor alarm for channels 3 & 4. 3, 7 mlotc[3:4] mask loss of transmit clock alarm for channels 3 & 4.
data sheet T7689 5.0 v t1 quad line interface may 1998 24 lucent technologies inc. microprocessor interface (continued) microprocessor interface register architecture (continued) global control register overview (0100, 0101) the bits in the global control registers in table 16 and table 17 allow the microprocessor to con?ure the various device functions over all the four channels. all the control bits (with the exception of losstd and ictmode) are active-high. these are read/write registers. table 16. global control register (0100) bits symbol description global control register (4) 0 gmask the gmask bit globally masks all the channel alarms when gmask = 1, pre- venting all the receiver and transmitter alarms from generating an interrupt. gmask = 1 after a device reset. 1 swreset the swreset provides the same function as the hardware reset. it is used for device initialization through the microprocessor interface. the software reset bit does not have a powerup default state; therefore, the ?st write to the device must clear this bit. 2 losstd the losstd bit selects the conformance protocol for the dlos receiver alarm function. 3 ictmode the ictmode bit changes the function of the ict pin. ictmode = 0 after a device reset. 4? highz[1:4] a highz bit is available for each individual channel. when highz = 1, the ttip and tring transmit drivers for the speci?d channel are placed in a high-impedance state. highz[1:4] = 1 after a device reset. table 17. global control register (0101) bits symbol description global control register (5) 0 cdr the cdr bit is used to enable and disable the clock/data recovery function. 1 jar the jar is used to enable and disable the jitter attenuator function in the receive path. the jar and jat control bits are mutually exclusive; i.e., either jar or the jat control bit can be set, but not both. 2 jat the jat is used to enable and disable the jitter attenuator function in the trans- mit path. the jat and jar control bits are mutually exclusive; i.e., either jat or the jar control bit should be set, but not both. 3 code the code bit is used to enable and disable the b8zs/hdb3 zero substitution coding (decoding) in the transmit (receive) path. it is used in conjunction with the dual bit and is valid only for single-rail operation. 4 dual the dual bit is used to select single or dual-rail mode of operation. 5 alm the alm bit selects the transmit and receive data polarity (i.e., active-low or active-high). the alm and acm bits are used together to determine the trans- mit and receive data retiming modes. 6 acm the acm bit selects the positive or negative edge of the receive clock (rclk[1:4]) for receive data retiming. the acm and alm bits are used together to determine the transmit and receive data retiming modes. 7 lossd the lossd bit selects the shutdown function for the digital loss of signal alarm (dlos).
data sheet may 1998 T7689 5.0 v t1 quad line interface 25 lucent technologies inc. microprocessor interface (continued) microprocessor interface register architecture (continued) channel con?uration register overview (0110?001) the control bits in the channel con?uration registers in table 18 are used to select equalization, loopbacks, ais generation, channel alarm masking, and the channel powerdown mode for each channel (1?). the pwrdn[1?], mask[1?], and tbs[1?] bits are active-high. these are read/write registers. * a numerical suf? identi?s the channel number. ? channel suf? not shown in the description. other registers the software reset bit must be cleared after powerup prior to writing any other bits in register 4. the bits in registers 10 and 11 must be written to all zeros after a device powerup. table 18. channel con?uration registers bits symbol * description ? channel con?uration registers (6?) 0 pwrdn[1:4] the pwrdn bit powers down a channel when not used. 1 mask[1:4] the mask bit masks all interrupts for the channel. 2 tbs[1:4] the tbs bit enables transmission of an all 1s signal to the line interface. 3, 4 loopb[1:4], loopa[1:4] the loopb and loopa bits select the channel loopback modes. 5, 6, 7 eqc[1:4], eqb[1:4], eqa[1:4] the eqc, eqb, and eqa bits select the associated transmitter cable equalization/termination impedances.
data sheet T7689 5.0 v t1 quad line interface may 1998 26 lucent technologies inc. microprocessor interface (continued) i/o timing the i/o timing speci?ations for the microprocessor interface are given in table 19. the microprocessor interface pins use cmos i/o levels. all outputs, except the address/data bus ad[7:0], are rated for a capacitive load of 50 pf. the ad[7:0] outputs are rated for a 100 pf load. the minimum read and write cycle time is 200 ns for all device con?urations. the read and write timing diagrams for all four microprocessor interface modes are shown in figures 4?1. table 19. microprocessor interface i/o timing speci?ations symbol con?uration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t1 modes 1 & 2 address valid to as asserted (read, write) 15 t2 as asserted to address invalid (read, write) 10 t3 as asserted to ds asserted 50 t4 r/ w high (read) to ds asserted 25 t5 ds asserted (read, write) to dtack asserted 20 t6 dtack asserted to data valid (read) 70 t7 ds asserted (read) to data valid 90 t8 ds negated (read, write) to as negated 25 t9 ds negated (read) to data invalid 15 t10 ds negated (read) to dtack negated 15 t11 as (read, write) asserted width 150 t12 ds (read) asserted width 100 t13 as asserted to r/ w low (write) 25 t14 r/ w low (write) to ds asserted 25 t15 data valid to ds negated (write) 25 t16 ds negated to dtack negated (write) 20 t17 ds negated to data invalid (write) 25 t18 ds (write) asserted width 100 t19 modes 3 & 4 address valid to ale asserted low (read, write) 15 t20 ale asserted low (read, write) to address invalid 10 t21 ale asserted low to rd asserted (read) 30 t22 rd asserted (read) to data valid 90 t23 rd asserted (read) to rdy asserted 75 t24 rd negated to data invalid (read) 20 t25 rd negated to rdy negated (read) 25 t26 ale asserted low to wr asserted (write) 30 t27 cs asserted to rdy asserted low 16 t28 data valid to wr negated (write) 25 t29 wr asserted (write) to rdy asserted 73 t30 wr negated to rdy negated (write) 22 t31 wr negated to data invalid 25 t32 ale asserted (read, write) width 150 t33 rd asserted (read) width 100 t34 wr asserted (write) width 100
data sheet may 1998 T7689 5.0 v t1 quad line interface 27 lucent technologies inc. microprocessor interface (continued) i/o timing (continued) 5-3685(c)r.6 figure 4. mode1?ead cycle timing (mpmode = 0, mpmux = 0) 5-3686(c)r.6 figure 5. mode1?rite cycle timing (mpmode = 0, mpmux = 0) t6 t7 t5 ds as cs minimum read cycle valid address valid data a[3:0] r/w t2 t1 t3 t10 t9 t8 t4 t12 ad[7:0] dtack t11 t14 t5 t15 ds as cs minimum write cycle valid address valid data a[3:0] r/w t2 t1 t13 t16 t17 t8 t18 ad[7:0] dtack t11
data sheet T7689 5.0 v t1 quad line interface may 1998 28 lucent technologies inc. microprocessor interface (continued) i/o timing (continued) 5-3687(c)r.9 figure 6. mode2?ead cycle timing (mpmode = 0, mpmux = 1) 5-3688(c)r.9 figure 7. mode2?rite cycle timing (mpmode = 0, mpmux = 1) valid address valid address valid data ds as cs minimum read cycle r/w ad[7:0] dtack t11 valid data t7 t9 t8 t2 t5 t1 t10 t12 t4 t3 t6 valid address valid address valid data ds as cs minimum write cycle r/w ad[7:0] dtack t11 valid data t17 t15 t8 t2 t5 t1 t16 t18 t14 t13
data sheet may 1998 T7689 5.0 v t1 quad line interface 29 lucent technologies inc. microprocessor interface (continued) i/o timing (continued) 5-3689(c)r.6 figure 8. mode3?ead cycle timing (mpmode = 1, mpmux = 0) 5-3690(c)r.7 figure 9. mode3?rite cycle timing (mpmode = 1, mpmux = 0) minimum read cycle t32 valid address ale cs a[3:0] rd ad[7:0] rdy valid data t23 t25 t24 t22 t19 t20 t33 t27 t21 minimum write cycle t32 valid address ale cs a[3:0] wr ad[7:0] rdy valid data t29 t30 t28 t19 t20 t34 t27 t26 t31
data sheet T7689 5.0 v t1 quad line interface may 1998 30 lucent technologies inc. microprocessor interface (continued) i/o timing (continued) 5-3691(c)r.9 figure 10. mode4?ead cycle timing (mpmode = 1, mpmux = 1) 5-3692(c)r.10 figure 11. mode4?rite cycle timing (mpmode = 1, mpmux = 1) minimum read cycle t32 t21 t33 t24 t27 t23 t25 t19 t20 valid data valid address valid data valid address rdy rd ale cs t22 ad[7:0] minimum write cycle t32 t26 t34 t31 t27 t29 t30 t19 t20 valid data valid address valid data valid address rdy wr ale cs t28 ad[7:0]
data sheet may 1998 T7689 5.0 v t1 quad line interface 31 lucent technologies inc. xclk reference clock the device requires a high-frequency reference clock for both clock/data recovery and jitter attenuation options (cdr = 1, jar = 1, or jat = 1). the xclk signal (pin 29) is conditionally required if the mpclk signal (pin 83) is not supplied for interrupt generation in the microprocessor interface. for any other device con?uration, xclk is not required. if it is required, xclk must be a continuously active (i.e., ungapped, unjittered, and unswitched) and an independent reference clock, such as an external system oscillator or system clock, for proper operation. it must not be derived from any recovered line clock (i.e., from rclk or any synthesized frequency of rclk). the speci? cations for xclk are de?ed in table 20. power supply bypassing external bypassing is required for all channels. a 1.0 m f capacitor must be connected between v dd x and gndx. in addition, a 0.1 m f capacitor must be connected between v ddd and gnd d , and a 0.1 m f capacitor must be con- nected between v dda and gnd a . ground plane connections are required for gndx, gnd d , and gnd a . power plane connections are also required for v dd x and v ddd . the need to reduce high-frequency coupling into the ana- log supply (v dda ) may require an inductive bead to be inserted between the power plane and the v dda pin of every channel. external bypassing is also required for the microprocessor power supply pins. a 0.1 m f capacitor must be con- nected between every pair of v ddc and gnd c pins. v ddc and gnd c are connected directly to the power and ground planes, respectively. capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum effectiveness. table 20. xclk timing speci?ations parameter value unit min typ max frequency: ds1 24.704 mhz range ?00 100 ppm duty cycle 40 60 %
data sheet T7689 5.0 v t1 quad line interface may 1998 32 lucent technologies inc. external line interface circuitry the transmit and receive tip/ring connections provide a matched interface to the cable (i.e., terminating impedance matches the characteristic impedance of the cable). the diagram in figure 12 shows the appropriate external com- ponents to interface to the cable for a single transmit/receive channel. the component values are summarized in table 21, based on the speci? application. 5-3693(c).dr.1 figure 12. external line termination circuitry * resistor tolerances are 1%. transformer turns ratio tolerances are 2%. ?a 5% tolerance is allowed for the transmit load termination. table 21. termination components by application * symbol name cable type unit twisted pair c c center tap capacitor 0.1 m f r p receive primary impedance 200 w r r receive series impedance 71.5 r s receive secondary impedance 113 z eq equivalent line termination 100 tolerance 4% r t transmit series impedance 0 w r l transmit load termination ? 100 n transformer turns ratio 1.14 rtip rring ttip tring device (1 channel) r l r s r r r r receive data r p z eq r t r t n:1 transmit data transformer equipment interface 1:n c c
data sheet may 1998 T7689 5.0 v t1 quad line interface 33 lucent technologies inc. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this device speci?ation. exposure to absolute maximum rat- ings for extended periods can adversely affect device reliability. table 22. absolute maximum ratings handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent technologies employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the de?ed model. no industry-wide stan- dard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters. operating conditions parameter min max unit dc supply voltage ?.5 6.5 v storage temperature ?5 125 c maximum voltage (digital pins) with respect to v ddd 0.5 v minimum voltage (digital pins) with respect to gnd d ?.5 v maximum allowable voltages (rtip[1?], rring[1?]) with respect to v dd 0.5 v minimum allowable voltages (rtip[1?], rring[1?]) with respect to gnd ?.5 v table 23. hbm esd threshold voltage device voltage T7689 >1500 v table 24. cdm esd threshold voltage device voltage T7689 >1500 v table 25. recommended operating conditions parameter symbol min typ max unit ambient temperature t a ?0 85 c power supply v dd 4.75 5.0 5.25 v
data sheet T7689 5.0 v t1 quad line interface may 1998 34 lucent technologies inc. operating conditions (continued) * a single channel (receive and transmit paths) for 50% ones density data. ? for standby purposes. if a channel will never be used, connecting all v dd pins to the ground plane is recommended, resulting in no power consumption. for nominal v dd , t a = 25 c. every function and channel operational with 50% ones density. for v dd = 5.25 v and t a = 25 c. every function and channel operational with 100% ones density. timing characteristics * 100 pf allowed for ad[7:0] (pins 69 to 76). table 26. power speci?ations (v dd = 5 v and t a = 25 c; device power speci?ation includes power to the line for a speci?d data ones density.) parameter T7689 unit per channel*: (typical) cdr = 0, jax = 0 (transmit, receiver in data slicing mode, no jitter attenuator) cdr = 1, jax = 0 (transmit, receiver in clock recovery mode, no jitter attenuator) cdr = 1, jax = 1 (transmit, receiver in clock recovery mode, jitter attenuator active) during powerdown mode (pwrdn = 1) ? 83 97 100 2.5 mw mw mw mw quad total: typical max 412 780 mw mw table 27. logic interface characteristics an internal 50 k w pull-up is provided on the ict and reset pins. an internal 100 k w pull-up is provided on the cs , xclk, and bclk pins. this requires these input pins to sink no more than 20 m a. all buffers use cmos levels. parameter symbol test conditions min max unit input voltage: low high v il v ih gnd d v ddd ?1.0 1.0 v ddd v v input leakage i l 1.0 m a output voltage: low high v ol v oh ?.0 ma 5.0 ma gnd d v ddd ?1.0 0.5 v ddd v v input capacitance c i 3.0 pf load capacitance* c l 50 pf
data sheet may 1998 T7689 5.0 v t1 quad line interface 35 lucent technologies inc. timing characteristics (continued) * refers to each individual bit period for jat = 0 applications. ? refers to each individual bit period for jat = 1 applications using a gapped tclk. 5-1156(c)r.8 * invert rclk for acm = 1. figure 13. interface data timing (acm = 0) table 28. interface data timing the digital system interface timing is shown in figure 13 for acm = 0. if acm = 1, then the rclk signal in figure 13 will be inverted. symbol parameter min typ max unit ttcltcl average tclk clock period: ds1 647.7 ns ttdc tclk duty cycle* tclk minimum high/low time ? 30 100 70 % ns ttdvtcl transmit data setup time 50 ns ttcltdx transmit data hold time 40 ns ttch1tch2 clock rise time (10%/90%) 40 ns ttcl2tcl1 clock fall time (90%/10%) 40 ns trchrcl rclk duty cycle 45 50 55 % trdvrch receive data setup time 140 ns trchrdx receive data hold time 180 ns trclrdv receive propagation delay 40 ns tclk tpdata or tndata rclk* rpdata or rndata ttcltcl ttch1tch2 ttcl2tcl1 ttdvtcl ttcltdx trclrdv trdvrch trchrdx
data sheet T7689 5.0 v t1 quad line interface may 1998 36 lucent technologies inc. outline diagram 100-pin bqfp dimensions are in millimeters. 5-1970(c).r10 detail a 0.255 0.91/1.17 gage plane seating plane pin #1 identifier zone 89 1 13 14 38 39 63 64 88 19.050 0.405 22.350 0.255 22.860 0.305 22.350 0.255 19.050 0.405 22.860 0.305 edge chamfer detail a 4.570 max detail b 0.760 0.255 0.635 typ 0.10 seating plane 3.555 0.255 detail b 0.280 0.075 0.150 m 0.175 0.025
data sheet may 1998 T7689 5.0 v t1 quad line interface 37 lucent technologies inc. ordering information ds98-232tic replaces ds96-185tic to incorporate the following updates 1. title corrected. 2. page 3, figure 1, corrected block diagram (single channel). 3. page 24, table 16, global control register (0100), added register address in table title. 4. page 24, table 17, global control register (0101), added register address in table title. 5. page 25, channel con?uration register overview (0110?001), corrected register address in section heading. 6. page 32, figure 12, external line termination circuitry, updated transformer. device code package temperature comcode (ordering number) t-7689 - - - fl - db 100-pin bqfp ?0 c to +85 c 107579625
data sheet T7689 5.0 v t1 quad line interface may 1998 copyright ?1998 lucent technologies inc. all rights reserved printed in u.s.a. may 1998 ds98-232tic (replaces ds96-185tic) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (bracknell), france: (33) 1 41 45 77 00 (paris), sweden: (46) 8 600 7070 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 2 6608131 (milan), spain: (34) 1 807 1441 (madrid) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. slc is a registered trademark of lucent technologies inc.


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